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Active-HDL 3.5 Active-CAD

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Draw state machines and data flow logic Identify bugs before generating HDL Develop hardware Generate VHDL and Verilog test benches

 
 
 
 

Web Resources

 The World Wide Web Virtual Library: The Z notation
 

Web Resources on VHDL, FPGA & Circuit Design
 

 VHDL Testbench Generator

 Reutilization of VHDL testbench and library components.

 VHDL Verification Course
 

 Web Resources on VHDL, FPGA & Circuit Design

http://www.optimagic.com

 OpenIPCore
 http://www.openip.org

 EDN Access--08.15.97 VHDL code implements 50%-duty-cycle divider

 TestBenchTool Easy Generation of Test Vectors for VHDL Designs

 Circuit Cookbook WWW page

 3rd Party Interfaces Aldec offers direct interfaces to IC Vendor and Logic Synthesis Partners based on TCL (Tool Command Language) and TK (User Interface) scripting language
 

VHDL TutorialClick on Image to Download